As a method for sharing a PCI Express device among a plurality of RCs, PCI-Special Interest Group (SIG), which is an industry standardization organization, has standardized multi-root I/O virtualization (MR-IOV) (for example, refer to Non-Patent Document 1).
FIG. 10 is a block diagram illustrating a basic configuration of MR-IOV. The MR-IOV is configured by a plurality of CPU/RCs 10-1, a multi-root aware PCI Express (PCIe) switch (MRA-SW) 10-2, a plurality of multi-root aware PCIe devices (MRA-DEVs) 10-3, and an MR-PCI manager (MR-PCIM) 10-4.
The MR-PCIM 10-4 is arranged on one of the CPU/RCs 10-1. Furthermore, the MR-PCIM 10-4 finds the topology and devices of the entire MR-IOV system, and sets the MRA-SW 10-2 based on a result thereof. Moreover, the MR-PCIM 10-4 sets the MRA-DEVs 10-3. As a result, the MRA-DEVs 10-3 can be simultaneously shared and used among the plurality of CPU/RCs 10-1.